1. Field of the Invention.
The present invention relates to timing synchronizing circuits for recovery of a clock signal and data from baseband data signals.
2. Technical Background
Common techniques for intelligence and data transmission depend upon a common timing standard between transmitting and receiving stations. Phase locked loops are widely used in circuits for recovery of clock signals from digital data signals, allowing expeditious synchronization of a receiving station including such a phase locked loop with the station transmitting the data signal. This eliminates the complication of providing an independent, synchronized clock in the receiving station. A classic phase locked loop configuration utilizes a phase comparator, filter and voltage controlled oscillator (VCO) coupled in a feedback loop configuration in such a way that the VCO generates an output signal of an appropriate frequency to decode the incoming data stream.
In a common form of baseband signaling, each unit of information corresponds to one cycle, or one clock pulse of the signal. Each unit of information is termed a bit and, as the signal, assumes one of a plurality of distinct voltage levels. Commonly, two signal voltage levels are used, arbitrarily designated "one" and "zero." The baseband signal assumes one of the two voltage levels during each clock pulse. The time duration of each clock pulse must be known to resolve or detect each bit of information received in a baseband signal. For example, where consecutive "ones" are received, no voltage level transition in the baseband signal occurs from one clock pulse to the next clock pulse. Without knowledge of the duration of the cycle, i.e. the bit length, it is impossible to determine how many "ones" (or "zeros") occurred during a period in which the baseband signal assumed a constant voltage level. Such a transmission system is also known as pulse code modulation.
Phase locked loops lock on the frequency of a signal with the strongest Fourier component, within the frequency band which is not rejected by filtering in the receiving unit. Where baseband is used to modulate a carrier, the phase locked loop can lock on to an independent clock signal transmitted with the modulated signal. In baseband signaling, however, the clock is determinable from voltage or logic level transitions of the baseband signal. In other words, some alternation in "ones" and "zeros" is necessary to resolve the clock. Attempts to apply prior art phase locked loops to baseband signaling formats have functioned properly only when there was a high probability of transitions between digital states of the signal.
Accordingly, it is desirable to provide a device which generates an accurate clock signal notwithstanding a relatively low probability in logic level transitions of a baseband data signal.